FIGS. 1A to 1D are configuration diagrams of a conventional semiconductor device in the form of a normal power MOSFET.
FIG. 1A is a plan view of the periphery of a section of aluminum gate wiring.
FIG. 1B is a sectional view (including a source region) when viewed along a section A-A'.
FIG. 1C is a sectional view (including a gate region) when viewed along a section B-B'.
FIG. 1D is a sectional view (including a source region and no P-type region) when viewed along a section A-A'.
Normally, the peripheral section of the aluminum gate wiring arranged on the surface of the semiconductor has a repetitive structure. A typical section is represented in FIG. 1A-1D.
On the surface of a MOSFET a high density silicon substrate 1 and a low density silicon substrate 2 act as a drain. A gate wiring under the P-type region 4 is formed by a special process under a gate wiring region (hereinafter referred to as a P-type region) positioned directly under a section of aluminum gate wiring 3.
The P-type region 4 provided on the upper surface of the silicon substrate 2 directly under the aluminum gate wiring 3 is formed continuously on the surface of the semiconductor, extending over the gate wiring in the wiring direction C (see FIGS. 1A and 1B).
Also, the P-type region 4 is connected to a section of aluminum source wiring 11 on the outer periphery (not shown) of the semiconductor device and has the same source potential.
Next, insulating oxidized gate films 5 are formed as insulating oxidized films, after which silicon gates 6 are formed.
After the desired patterning is performed, the silicon gates 6 are perforated by etching a unit cell portion.
A P-type base region 7 and a source region 8 are then formed by a self-aligning method to mask an open section of the silicon gate 6.
Finally, holes, specifically contact holes 10 and 12, are opened onto an insulating interlayer film 9 and the elements are connected through aluminum wiring.
The contact hole 10 connects the source region 8 and the P-type base region 7 of each unit cell to aluminum source wiring 11, and the contact hole 12 connects the silicon gate 6 to the aluminum gate wiring 3.
With the gate wiring under-structure of this conventional semiconductor device, the insulating oxidized gate film 5 is formed on the surface of the P-type region 4, and impurities from the P-type region 4 become incorporated in the insulating oxidized gate film 5 during various heating processes.
This creates the problem that the capability of an insulation voltage resistance of the insulating oxidized gate film 5 is reduced.
Normally, as shown in FIG. 1B, this problem is avoided by forming the insulating oxidized gate film 5 to an ample thickness in comparison with other film thicknesses by using a special process to selectively increase the film thickness. In FIG. 1B, a depletion layer is indicated by the reference number 13.
On the other hand, as shown in FIG. 1D, if the P-type region 4 is absent, a sudden change 14 in the curvature of a depletion layer 13 results because the under-section of the P-type region 4 would normally act as a connecting section for the depletion layer 13 which is formed on both sides of the P-type region 4.
Therefore, a localized breakdown is induced from electrostatic concentration so that the breakdown voltage (or a drain-source breakdown voltage between the drain section and the source section) is lowered.
As outlined above, with a conventional semiconductor device having tile configuration described above, the problem arises that the insulation voltage resistance of the insulating oxidized gate film 5 is reduced.
This problem is avoided by forming the insulating oxidized gate film 5 to an ample thickness in comparison with other film thicknesses, like the thicker P-type region 4 shown in FIG. 1C. However, a special process is necessary to selectively increase the film thickness, which is also a problem.
In addition, as shown in FIG. 1D, in the case where there is no P-type region directly under the aluminum gate wiring, a sudden change 14 is caused in the curvature of the depletion layer 13 so that the breakdown voltage (or the drain-source breakdown voltage) is lowered.